1. Field of the Invention
The present invention relates to the field of integrated circuit (IC). More specifically, the present invention relates to the architecture of reconfigurable ICs.
2. Background Information
The art of design and manufacturing ICs is generally known. Over the years, as the technology of designing and manufacturing ICs continues to improve, increasing number of electronic elements are being packed into a single IC, and the interrelationship between these elements are increasingly complex. With increased density and complexity, the cost for making an IC manufacturing mask has increased substantially correspondingly.
Between different offerings of a modern IC product family, or between successive offerings, often times the functionalities are different only in a relatively small incremental way, when viewed in the context of the totality of its logic. Thus, in view of the high cost of a new IC mask as well as other factors, increasingly IC designers desire to have ICs that are partially reconfigurable to accommodate the small incremental changes in functionalities between the different offerings.
U.S. Pat. No. 5,574,388 discloses a reconfigurable IC designed for emulation application. The architecture including in particular the integrated debugging facilities was particularly suitable for the intended use. However, general purpose partially reconfigurable integrated circuits present a different set of challenges. One desirable attribute is scalability to provide more flexible tradeoffs between area consumption versus routability.
Thus, an improved reconfigurable IC architecture is desired.
An integrated circuit (IC) includes a number of function blocks, of which at least one is a reconfigurable function block. Each function block may be a reconfigurable function, a non-reconfigurable function or recursively expanded with additional xe2x80x9cnestedxe2x80x9d function blocks interconnected with the same architecture. The IC further includes a number of external input pins, and a number of external output pins.
The elements, at least at the IC level, are coupled in a manner such that all input signals are routed from the external input pins to the function blocks through a first subset of crossbar devices, all internal signals are routed from one function block to another function block through a second subset of crossbar devices, and all output signals are routed from the function blocks to the external output pins through a third subsets of crossbar devices.
In one embodiment each crossbar device output has a single fanout. Additionally, each crossbar device may provide only one input to another crossbar device.